| 摘要 |
A device for testing and monitoring digital circuits for detecting timing faults affecting a signal D received directly at the input of a flip-flop called primary sampling element, supplying a first value D1 of the signal D and receiving a first clock signal, including at least: a scan logic module having a first input receiving the signal “D”, a second input receiving a “scan in” signal and a third input receiving a “scan enable” signal suitable for selecting the operating mode of the testing device in a scan mode or an operational mode, and an output linked to a secondary sampling element supplying a second sampled signal D2 of the signal D after passing through the scan logic module, and receiving a second clock signal; a module for comparison of the signal D1 and the signal D2 generating an alert or error signal. |
