发明名称 BUFFER CIRCUIT HAVING ENHANCED SLEW-RATE AND SOURCE DRIVING CIRCUIT INCLUDING THE SAME
摘要 Disclosed are a buffer circuit having an enhanced slew-rate and a source driving circuit including the same. The buffer circuit includes an operational amplifier and a slew-rate compensation circuit. The operational amplifier amplifies an input voltage signal and generates an output voltage signal. The slew-rate compensation circuit generates a compensation current based on a difference between the input voltage signal and the output voltage signal, provides the compensation current to the load stage of the operational amplifier, and reduces the transition time of the output voltage signal. Therefore, the output driving performance of a buffer circuit is improved and power consumption is reduced.
申请公布号 KR20150033161(A) 申请公布日期 2015.04.01
申请号 KR20130112790 申请日期 2013.09.23
申请人 发明人
分类号 G09G3/36 主分类号 G09G3/36
代理机构 代理人
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