| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To provide a comparator circuit that implements higher speed and lower power consumption than prior art. <P>SOLUTION: The comparator circuit includes: an input differential pair and adaptive bias current generation circuit for generating an adaptive bias current in response to two input voltages input thereinto at either MOS transistor of an input differential pair of first and second MOS transistors in a loop including the one MOS transistor and a switch transistor; and a latch circuit for detecting a current corresponding to the adaptive bias current to change latch logic, and then switching the switch transistor from an on state to an off state to cut off the adaptive bias current. <P>COPYRIGHT: (C)2013,JPO&INPIT</p> |
