发明名称 パルス幅変調回路
摘要 <p><P>PROBLEM TO BE SOLVED: To prevent generation of noise when an input signal is zero, and synchronize two pulse width modulation signals without using an external clock. <P>SOLUTION: A first monostable multivibrator charges a capacitor Ca with a first charging current in response to a high level of a clock signal and stops the charging when a charging voltage reaches a threshold voltage, and outputs a first pulse signal in accordance with the charging action. A second monostable multivibrator charges a capacitor Cb with a second charging current in response to the high level of the clock signal and stops the charging when a charging voltage reaches the threshold voltage, and outputs a second pulse signal in accordance with the charging action. A clock signal generating monostable multivibrator charges a capacitor Cc with the second charging current in response to a low level of the first pulse signal and stops the charging when a charging voltage reaches the threshold voltage, and outputs the clock signal in accordance with the charging action. <P>COPYRIGHT: (C)2013,JPO&INPIT</p>
申请公布号 JP5692038(B2) 申请公布日期 2015.04.01
申请号 JP20110275064 申请日期 2011.12.15
申请人 发明人
分类号 H03K7/08;H03F3/217 主分类号 H03K7/08
代理机构 代理人
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