发明名称 |
Semiconductor integrated circuit device |
摘要 |
A semiconductor integrated circuit device includes a first flip-flop circuit receiving data in synchronization with a first clock signal, a logic circuit performing a predetermined process on data output from the first flip-flop circuit, a hold buffer delaying transmission of an output of the logic circuit, a second flip-flop circuit receiving an output of the hold buffer in synchronization with a second clock signal, and a power supply circuit capable of selecting a supply of a power supply voltage to the first flip-flop circuit, the logic circuit, and the second flip-flop circuit between a first power supply voltage and a second power supply voltage higher than the first power supply voltage. A power supply voltage supplied to the hold buffer remains the same when the power supply voltage supplied to the first flip-flop circuit, the logic circuit, and the second flip-flop circuit changes between first and second power supply voltages. |
申请公布号 |
US8994405(B1) |
申请公布日期 |
2015.03.31 |
申请号 |
US201414191327 |
申请日期 |
2014.02.26 |
申请人 |
Kabushiki Kaisha Toshiba |
发明人 |
Suzuki Azuma;Hara Hiroyuki |
分类号 |
H03K19/00;H03K19/003 |
主分类号 |
H03K19/00 |
代理机构 |
Patterson & Sheridan, LLP |
代理人 |
Patterson & Sheridan, LLP |
主权项 |
1. A semiconductor integrated circuit device comprising:
a first flip-flop circuit configured to receive data in synchronization with a first clock signal; a logic circuit configured to perform a predetermined process on data output from the first flip-flop circuit; a hold buffer circuit configured to delay transmission of an output of the logic circuit; a second flip-flop circuit configured to receive an output of the hold buffer circuit in synchronization with a second clock signal; and a power supply circuit configured to select a supply of a power supply voltage to the first flip-flop circuit, the logic circuit, and the second flip-flop circuit between a first power supply voltage and a second power supply voltage higher than the first power supply voltage, wherein a power supply voltage supplied to the hold buffer circuit remains the same even when the power supply voltage supplied to the first flip-flop circuit, the logic circuit, and the second flip-flop circuit changes between the first and second power supply voltages. |
地址 |
Tokyo JP |