Dual-port SRAM systems

摘要

Schematic circuit designs for a dual-port SRAM cell are disclosed, together with various layout schemes for the dual-port SRAM cell. The dual-port SRAM cell comprises a storage unit and a plurality of partial dummy transistors connected to the outputs of the storage unit. Various layout schemes for the dual-port SRAM cell are further disclosed. A gate electrode serves as the gate for a pull-down transistor and a pull-up transistor, a gate of a first partial dummy transistor, and a gate of a second partial dummy transistor. A butt contact connects a long contact to the gate electrode. The long contact further connects to a drain of a pull-down transistor, a drain of a pull-up transistor, a drain of a first pass gate, and a drain of a second pass gate, wherein the first pass gate and the second pass gate share an active region.

主权项

1. A device comprising:
a data latch storage unit comprising a first inverter having a first output and a first input, and a second inverter having a second output directly coupled to the first input, and a second input directly coupled to the first output, the second output being a complement of the first output; a first dummy circuit comprising a first plurality of dummy transistors connected to the first output; and a second dummy circuit comprising a second plurality of dummy transistors connected to the second output, wherein a respective one of the first plurality of dummy transistors and the second plurality of dummy transistors is formed in a respective active area of a substrate, and wherein an edge of the respective active area does not extend beyond a width of a gate electrode of the respective one of the first plurality of dummy transistors and the second plurality of dummy transistors.