Level shifter circuit optimized for metastability resolution and integrated level shifter and metastability resolution circuit

摘要

A level shifter and integrated level shifter and metastability resolution flop circuit are disclosed. A circuit includes a generation circuit, in a first voltage domain, coupled to receive a logic signal via a single-ended input and configured to generate true and complementary values of the logic signal. The circuit further includes a storage circuit coupled to receive the true and complementary values of the logic signal from the generation circuit. The storage circuit is configured to store the true and complementary values of the logic signal. The storage circuit is in a second voltage domain. The circuit further includes an output circuit coupled to the storage circuit and configured to provide a differential output signal having true and complementary values corresponding to the true and complementary values of the logic signal. The circuit may be combined with a latch circuit coupled to receive the differential output signal.

主权项

1. A circuit comprising:
a generation circuit in a first voltage domain and coupled to receive a logic signal via a single-ended input and configured to generate true and complementary values of the logic signal on true and complementary input nodes, respectively; a storage circuit coupled to receive the true and complementary values of the logic signal from the generation circuit, wherein the storage circuit is configured to store the true and complementary values of the logic signal, wherein the storage circuit is in a second voltage domain having a second operating voltage, wherein the storage circuit includes a first internal state node and a second internal state node; an output circuit coupled to the storage circuit and configured to provide a differential output signal having true and complementary values corresponding to the true and complementary values of the logic signal; a first pull-up transistor coupled between the first internal state node and a voltage supply node of the second voltage domain, wherein the first pull-up transistor includes a gate terminal coupled to the true input node; and a second pull-up transistor coupled between the second internal state node and the voltage supply node of the second voltage domain, wherein the second pull-up transistor includes a gate terminal coupled to the complementary input node.