发明名称 Load transient detection and clock reset circuit
摘要 A switching regulator comprises a PWM controller that controls switching of a power converter via a PWM control signal. The switching regulator detects load transients in the load driven by the power converter. Responsive to the detection of a load transient, the switching regulator resets a PWM clock synchronously with a fast clock operating at a higher frequency than the PWM clock. By doing so, the switching regulator beneficially responds more quickly to changes in the load than with conventional architectures that utilize only the slower PWM clock. This provides improved transient response without sacrificing power efficiency.
申请公布号 US8994350(B2) 申请公布日期 2015.03.31
申请号 US201012946662 申请日期 2010.11.15
申请人 Dialog Semiconductor Inc. 发明人 Li Yang
分类号 H02M3/158;H02M3/156 主分类号 H02M3/158
代理机构 Fenwick & West LLP 代理人 Fenwick & West LLP
主权项 1. A switching regulator, comprising: a PWM controller configured to receive a PWM clock signal and generate a PWM control signal based on the PWM clock signal; a power converter configured to receive the PWM control signal from the PWM controller and provide regulated power to a load, the regulated power controllable by varying a duty cycle of the PWM control signal; a load transient detection circuit configured to detect an increase in load exceeding a detection threshold and assert a load transient detection signal responsive to detecting the increase in load exceeding the detection threshold; and clock reset logic to assert a clock reset signal responsive to the load transient detection signal being asserted; and a clock divider coupled to the clock reset logic, the clock divider to receive a fast clock signal and divide a frequency of the fast clock signal to generate the PWM clock signal, the PWM clock signal having a lower frequency than the fast clock signal, wherein responsive to the clock reset signal being asserted, the clock divider resets the PWM clock signal to synchronize a next clock cycle of the PWM clock signal with a next clock cycle of the fast clock signal occurring after the clock reset signal is asserted, and wherein the clock divider is further configured to continue to generate new clock cycles of the PWM clock signal at the PWM clock frequency after resetting the PWM clock signal.
地址 Campbell CA US