Method and apparatus for multiply instructions in data processors

摘要

The disclosed embodiments relate to apparatus for accurately, efficiently and quickly executing a multiplication instruction. The disclosed embodiments can provide a multiplier module having an optimized layout that can help speed up computation of a result during a multiply operation so that cycle delay can be reduced and so that power consumption can be reduced.

主权项

1. A multiplier module for digitally multiplying a multiplicand operand by a multiplier operand, comprising:
a partial product array having a folded layout that is split into a low-side and a high-side, comprising:
a plurality of booth encoders that are each configured to generate a particular select signal based on a portion of the multiplier operand, wherein the plurality of booth encoders are arranged along a substantially diagonal path that extends between the high-side and the low-side;a plurality of booth multiplexers that collectively generate a plurality of partial products based on the multiplicand operand and the select signals generated by the booth encoders; anda carry-save adder array comprising: a plurality of compressor levels that are interleaved with the plurality of booth multiplexers.