发明名称 Memory system and bank interleaving method
摘要 According to embodiments, a memory system includes a plurality of memory chips configuring banks, an instruction generator, and a memory controller. The instruction generator generates a plurality of instructions. The memory controller is configured to execute memory accesses to the banks based on the instructions. Each memory access comprises a first command sequence and a second command sequence. The first command sequence causes in-bank processing shortly subsequent to the first command. The second command sequence is executed subsequent to the in-bank processing. The memory controller executes successively a second command sequence to a first bank based on a first instruction and a first command sequence to the first bank based on a second instruction subsequent to the first instruction, and then starts a memory access to a second bank based on a third instruction while the first bank is executing the in-bank processing caused by the first command sequence.
申请公布号 US8996782(B2) 申请公布日期 2015.03.31
申请号 US201213600578 申请日期 2012.08.31
申请人 Kabushiki Kaisha Toshiba 发明人 Ide Takashi;Iwasaki Kiyotaka;Watanabe Kouji;Nanjou Hiroyuki;Moriya Makoto
分类号 G06F12/06;G06F13/14 主分类号 G06F12/06
代理机构 Oblon, McClelland, Maier & Neustadt, L.L.P. 代理人 Oblon, McClelland, Maier & Neustadt, L.L.P.
主权项 1. A memory system comprising: non-transitory semiconductor memory; and a controller configured to control the non-transitory semiconductor memory, wherein the controller comprises: a first command queue; a second command queue having a higher priority than the first command queue; and a processor configured to select either the first command queue or the second command queue and to execute a command stored in the selected command queue thereby to access the non-transitory semiconductor memory, the processor executing either interruption processing of interrupting execution of the first command and executing the second command or completion processing of completing execution of the first command according to an access progress situation of the first command to the non-transitory semiconductor memory at a timing when the second command is stored in the second command queue, when the second command is stored in the second command queue while the first command stored in the first command queue is being executed.
地址 Tokyo JP