Memory reorder queue biasing preceding high latency operations

摘要

A method for controlling memory refresh operations in dynamic random access memories. The method includes determining a count of deferred memory refresh operations for a first memory rank. Responsive to the count approaching a high priority threshold, issuing an early high priority refresh notification for the first memory rank, which indicates the pre-determined time for performing a high priority memory refresh operation at the first memory rank. Responsive to the early high priority refresh notification, the behavior of a read reorder queue is dynamically modified to give priority scheduling to at least one read command targeting the first memory rank, and one or more of the at least one read command is executed on the first memory rank according to the priority scheduling. Priority scheduling removes these commands from the re-order queue before the refresh operation is initiated at the first memory rank.

主权项

1. A method of operating a memory system, the method comprising:
a memory controller tracking a time remaining before a scheduled time for initiating a high priority, high latency operation to a first memory rank of the memory system, wherein a plurality of memory ranks are individually accessible by different memory access operations scheduled from a command re-order queue of the memory controller, wherein the scheduled time of the high priority, high latency operation is a future time, and wherein the command re-order queue contains memory access operations targeting the plurality of memory ranks; in response to the time remaining reaching a pre-established early notification time before the schedule time for initiating the high priority, high latency operation:
biasing the re-order queue to prioritize scheduling of any first memory access operations that target the first memory rank; andscheduling the first memory access operations to the first memory rank for early completion relative to other memory access operations in the command re-order queue that target other memory ranks of the plurality of memory ranks, wherein the scheduling of the first memory access operations to the first memory rank for early completion causes the first memory access operations to be completed before performing the high priority, high latency operation at the first memory rank; and performing the high priority, high latency operation at the first memory rank at the scheduled time; wherein the biasing of the command re-order queue and scheduling of the first memory access operations triggers a faster depletion of first memory access commands remaining within the command re-order queue before the high priority, high latency operation is performed at the first memory rank.