Error correction code rate management for nonvolatile memory

摘要

An apparatus having an interface and a circuit is shown. The interface is coupled to a memory that is nonvolatile. The circuit is configured to (i) read a plurality of codewords from a block in the memory based on a program/erase count associated with the block, (ii) count a number of iterations used to decode the codewords and (iii) decrease a code rate of an error correction coding used to program the block in response to the number of iterations exceeding a threshold.

主权项

1. An apparatus comprising:
an interface configured to process a plurality of read/write operations to/from a memory; and a control circuit configured to (i) read all codewords from a block in the memory in response to one or more trigger events, wherein the trigger events occur when (a) a program/erase count of the block reaches a predetermined value and (b) a predetermined time elapses since a previous trigger event and before the program/erase count reaches the predetermined value, (ii) count a number of iterations used to decode the codewords read from the block and (iii) decrease a code rate of an error correction coding used to program the block where the number of iterations exceeds a threshold.