Data transfer operation completion detection circuit and semiconductor memory device provided therewith

摘要

A data transfer operation completion detection circuit including a first counter for performing a shifting operation in response to the generation of a read initiation signal, a second counter for performing a shifting operation in response to the generation of a burst completion signal, and an SR latch circuit for generating a read enable signal in response to the burst completion signal being generated when the count value of the first counter matches the count value of the second counter. The completion of a read operation or another data transfer operation is thus detected based on a read initiation signal reception history; therefore, it is possible to detect whether all read operations are complete at a given time even if a new read command is received while a read operation or the like is in progress.

主权项

1. A method for entering a power down mode in a semiconductor device, the method comprising:
initializing a first counter to a first initial state; initializing a second counter to a second initial state; receiving, at a first time, an enable signal having a first logic level to enable data transfer operations; receiving a first data transfer command; incrementing the first counter in response to the first data transfer command; receiving, at a second time, the enable signal having a second logic level opposite the first logic; transferring first data in response to the first data transfer command; incrementing the second counter upon completion of the first data transfer; and entering the power down mode in response to the enable signal having the second logic level and the first counter having a same state as the second counter.