System and method for powering a timer using a low current linear regulator during hibernate mode while disabling a switching power supply associated with powering a processor responsible for setting a hibernate enable bit

摘要

A Multi-Tile Power Management Integrated Circuit (MTPMIC) includes tiles including an MCU/ADC tile and a power manager tile. The power manager tile includes a hibernate circuit and a set of Configurable Switching Power Supply Pulse Width Modulator (CSPSPWM) components. The CSPSPWM, in combination with other circuitry external to the integrated circuit, form a switching power supply. The hibernate circuit is operable in a hibernate mode where the CSPSPWM is disabled and the switching power supply no longer generates a supply voltage. A processor in the MCU/ADC tile writes across a standardized bus to configure the hibernate circuit to wake up after a timer determines a configurable amount of time has lapsed, or to wake up in response to a signal present on a terminal of MTPMIC. The processor enables the hibernate mode causing the switching power supply to no longer provide power to the processor and other circuitry of MTPMIC.

主权项

1. An integrated circuit comprising:
a Configurable Switching Power Supply Pulse Width Modulator (CSPSPWM), wherein the CSPSPWM is part of a switching power supply that generates a supply voltage from a power source, and wherein the CSPSPWM includes a low current linear regulator supplied by a current directly from the power source; a hibernate circuit, wherein the hibernate circuit includes a timer, and wherein the hibernate circuit is operable in a hibernate mode in which the hibernate circuit disables the CSPSPWM and uses power supplied from the low current linear regulator to power the timer; a configuration register, wherein the configuration register has a hibernate mode enable bit; and a processor that is powered by the supply voltage generated by the switching power supply, wherein the processor is configured to write to the configuration register thereby causing the hibernate mode enable bit to be set such that the hibernate mode is enabled, and wherein an event signal causes the hibernate mode enable bit to be set such that the hibernate mode is disabled.