Method, apparatus, and system for energy efficiency and energy conservation including optimizing C-state selection under variable wakeup rates

摘要

A processor may include power management techniques to, dynamically, chose an optimal C-state for the processing core. The measurement of real workloads on the OSes exhibit two important observations (1) the bursts of high interrupt rate are interspersed between the low interrupt rate periods and long periods of high activity levels; and (2) the interrupt rate may, suddenly, fall below an interrupt rate (of 1 milli-second, for example) that is typical of the current operating systems (OS). Instead of determining the C-state based on the stale data stored in the counters, the power control logic may determine an optimal C-state by overriding the C-state determined by the OS or any other power monitoring logic. The power control logic may, dynamically, determine an optimal C-state based on the CPU idle residency times and variable rate wakeup events to match the expected wakeup event rate.

主权项

1. A processor comprising:
a plurality of processing cores; at least one cache memory; and a power management unit to receive a first request from an operating system for entry into a first power saving state into which the processor is to be placed, demote the processor to a second power saving state, which is a lesser power saving state than the first power saving state if a low activity period of the processor overlaps with a burst of high interrupt rate, and un-demote the processor to a third power saving state, which is a greater power saving state than the first power saving state in response to a determination that an interrupt rate is low, without receipt of an interrupt from the operating system.