Performing emulated message signaled interrupt handling

摘要

In an embodiment, a processor includes a logic to store a write transaction including an interrupt and data received from a device coupled to the processor to a cache line of a cache memory based on an address in an address queue, and forward an address of the cache line and assert an emulated message signaling interrupt (MSI) signal to an interrupt controller of the processor. Other embodiments are described and claimed.

主权项

1. A processor comprising:
a first logic to store a write transaction including an interrupt and data received from a device coupled to the processor to a cache line of a cache memory based on an address in an address queue, and forward an address of the cache line and assert an emulated message signaling interrupt (MSI) signal to an interrupt controller of the processor; the interrupt controller coupled to the first logic to obtain the data stored in the cache line responsive to the emulated MSI signal and to assign at least one interrupt vector of the data to a first core of the processor to cause the first core to handle the interrupt; and the first core coupled to the interrupt controller and including at least one execution unit to perform operations responsive to an interrupt handler accessed via the at least one interrupt vector.