APPARATUS AND METHODS FOR SYNCHRONIZING PHASE-LOCKED LOOPS

摘要

Apparatus and methods for synchronizing phase-locked loops (PLLs) are provided. In certain implementations, a fractional-N synthesizer includes a PLL and a control circuit that controls a division value of the PLL. The control circuit includes an interpolator, a reset phase adjustment calculator, and a synchronization circuit. The interpolator can control a fractional portion of the PLL's division value. The reset phase adjustment calculator can include a counter for counting a number of cycles of the reference clock signal since initialization of the fractional-N synthesizer, and the reset phase adjustment calculator can generate a phase adjustment signal based on the count. The synchronization circuit can synchronize the PLL in response to a synchronization signal, and can correct for a synchronization phase error indicated by the phase adjustment signal.

主权项

1. An apparatus comprising:
a first phase-locked loop (PLL) configured to receive a reference clock signal and to generate an output clock signal, wherein the first PLL comprises a programmable divider configured to receive a division signal, wherein a ratio of a frequency of the output clock signal to a frequency of the reference clock signal changes in relation to the division signal; a first control circuit configured to generate the division signal, wherein the first control circuit comprises:
an interpolator configured to generate an interpolated signal based on a fraction numerator signal and based on a modulus signal, wherein the first control circuit is configured to generate the division signal based on the interpolated signal;a reset phase adjustment calculator configured to generate a phase adjustment signal and to receive an initialization signal, wherein the reset phase adjustment calculator comprises a counter configured to count a number of periods of the reference clock signal, wherein the counter is configured to be reset by the initialization signal, and wherein the phase adjustment signal is based on a count of the counter; anda synchronization circuit configured to synchronize the first PLL in response to a synchronization signal, wherein the synchronization circuit is configured to correct for a synchronization phase error indicated by the phase adjustment signal.