| 发明名称 |
3D IC Testing Apparatus |
| 摘要 |
A method comprises connecting a testing setup having a plurality of probes to a device under test having a plurality of vias, wherein a probe is aligned with a corresponding via of the device under test and conducting a plurality of via electrical characteristic tests through a conductive path comprising the vias, the probes and a plurality of conductive devices, each of which connects two adjacent probes, wherein the conductive devices are in the testing setup. |
| 申请公布号 |
US2015087089(A1) |
申请公布日期 |
2015.03.26 |
| 申请号 |
US201414561442 |
申请日期 |
2014.12.05 |
| 申请人 |
Taiwan Semiconductor Manufacturing Company, Ltd. |
发明人 |
Wang Mill-Jer;Chen Chih-Chia;Lin Hung-Chih;Peng Ching-Nen;Chen Hao |
| 分类号 |
G01R31/28;G01R1/073;H01L21/66 |
主分类号 |
G01R31/28 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. A method comprising:
connecting a testing setup having a plurality of probes to a device under test having a plurality of vias, wherein a probe is aligned with a corresponding via of the device under test; and conducting a plurality of via electrical characteristic tests through a conductive path comprising the vias, the probes and a plurality of conductive devices, each of which connects two adjacent probes, wherein the conductive devices are in the testing setup. |
| 地址 |
Hsin-Chu TW |
