Protocol For Refresh Between A Memory Controller And A Memory Device

摘要

The present embodiments provide a system that supports self-refreshing operations in a memory device. During operation, the system transitions the memory device from an auto-refresh state, wherein a memory controller controls refreshing operations for the memory device, to a self-refresh state, wherein the memory device controls the refreshing operations. While the memory device is in the self-refresh state, the system sends progress information for the refreshing operations from the memory device to the memory controller. Next, upon returning from the self-refresh state to the auto-refresh state, the system uses the progress information received from the memory device to control the sequencing of subsequent operations by the memory controller.

主权项

1. A memory controller integrated circuit to control a dynamic random access memory device (DRAM) having first and second banks each bank containing an array of DRAM memory cells, the memory controller integrated circuit comprising:
a first interface to output a first memory command to the DRAM via a first communications link; a second interface to output a second memory command to the DRAM via a second communications link; and wherein the first command is used to initiate a refresh operation to the first bank of the DRAM via the first interface and the second command is used to initiate a memory operation to a second bank of the DRAM via the second interface the second command being initiated concurrent with performance of the refresh operation in the first bank.