发明名称 SEMICONDUCTOR DEVICE INCLUDING HEAT DISSIPATING STRUCTURE
摘要 A semiconductor device includes a substrate serving as a base and having a surface on which electrodes are provided, a semiconductor chip mounted to the surface of the substrate, a sealing portion sealing the semiconductor chip and the surface of the substrate, first vias each penetrating the sealing portion in a thickness direction of the sealing portion to reach the electrodes on the surface of the substrate, external terminals connected to the first vias, and second vias provided near the semiconductor chip, extending to such a depth that the second vias do not penetrate the sealing portion, and insulated from the substrate and the semiconductor chip.
申请公布号 US2015084180(A1) 申请公布日期 2015.03.26
申请号 US201414558638 申请日期 2014.12.02
申请人 PANASONIC CORPORATION 发明人 SEKO Koichi;OTANI Katsumi;MATSUMOTO Katsuyoshi
分类号 H01L23/367;H01L23/31;H01L23/00;H01L23/538 主分类号 H01L23/367
代理机构 代理人
主权项 1. A semiconductor device comprising: a base having a first surface, a second surface opposite to the first surface, and electrodes on the first surface; a first semiconductor chip mounted to the first surface of the base; a sealing portion sealing the first semiconductor chip and the first surface of the base; a plurality of first vias penetrating the sealing portion from a surface of the sealing portion in a thickness direction of the sealing portion and each electrically connected to a corresponding one of the electrodes on the first surface of the base; a plurality of first external terminals provided on the surface of the sealing portion and each connected to a corresponding one of the first vias; a plurality of second vias located inwardly from the first vias and extending from the surface of the sealing portion in the thickness direction of the sealing portion to such a depth that the second vias do not penetrate the sealing portion; and a plurality of second external terminals provided on the surface of the sealing portion and each connected to a corresponding one of the second vias; wherein the second vias are not in contact with the first semiconductor chip.
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