发明名称 |
MANAGING HIGH-CONFLICT CACHE LINES IN TRANSACTIONAL MEMORY COMPUTING ENVIRONMENTS |
摘要 |
Cache lines in a computing environment with transactional memory are configurable with a coherency mode. Cache lines in full-line coherency mode are operated or managed with full-line granularity. Cache lines in sub-line coherency mode are operated or managed as sub-cache line portions of a full cache line. When a transaction accessing a cache line in full-line coherency mode results in a transactional abort, the cache line may be placed in sub-line coherency mode if the cache line is a high-conflict cache line. The cache line may be associated with a counter in a conflict address detection table that is incremented whenever a transaction conflict is detected for the cache line. The cache line may be a high-conflict cache line when the counter satisfies a high-conflict criterion, such as reaching a threshold value. The cache line may be returned to full-line coherency mode when a reset criterion is satisfied. |
申请公布号 |
US2015089152(A1) |
申请公布日期 |
2015.03.26 |
申请号 |
US201314037879 |
申请日期 |
2013.09.26 |
申请人 |
International Business Machines Corporation |
发明人 |
Busaba Fadi Y.;Cain, III Harold W.;Gschwind Michael K.;Michael Maged M.;Salapura Valentina;Schwarz Eric M.;Shum Chung-Lung K. |
分类号 |
G06F12/08 |
主分类号 |
G06F12/08 |
代理机构 |
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代理人 |
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主权项 |
1. A method for reducing transaction conflicts in a computing environment with transactional memory, the computing environment including a cache configured to hold a plurality of cache lines, each cache line configurable with a coherency mode, the method comprising:
executing a first transaction in the computing environment, the first transaction accessing a first cache line in a full-line coherency mode, wherein cache control logic associated with the cache is configured to operate or manage the first cache line in the full-line coherency mode with a full-line granularity; detecting a conflicting access of the first cache line while executing the first transaction, the conflicting access resulting in a transactional abort; based on the detecting, placing the first cache line in a sub-line coherency mode, wherein the cache control logic is configured to operate or manage a plurality of sub-cache line portions of the first cache line in the sub-line coherency mode; and executing a subsequent transaction in the computing environment, the subsequent transaction accessing and managing only a relevant sub-cache line portion of the first cache line in the sub-line coherency mode. |
地址 |
Armonk NY US |