Data Compression In Processor Caches

摘要

In an embodiment, a processor includes a cache data array including a plurality of physical ways, each physical way to store a baseline way and a victim way; a cache tag array including a plurality of tag groups, each tag group associated with a particular physical way and including a first tag associated with the baseline way stored in the particular physical way, and a second tag associated with the victim way stored in the particular physical way; and cache control logic to: select a first baseline way based on a replacement policy, select a first victim way based on an available capacity of a first physical way including the first victim way, and move a first data element from the first baseline way to the first victim way. Other embodiments are described and claimed.

主权项

1. A processor comprising:
a cache data array including a plurality of physical ways, each physical way to store a baseline way and a victim way; a cache tag array including a plurality of tag groups, each tag group associated with a particular physical way and including a first tag and a second tag, the first tag associated with the baseline way stored in the particular physical way, and the second tag associated with the victim way stored in the particular physical way; cache control logic to:
select a first baseline way based on a replacement policy;select a first victim way based on an available capacity of a first physical way including the first victim way; andmove a first data element from the first baseline way to the first victim way.