发明名称 MEMORY SYSTEM
摘要 According to an embodiment, a memory system includes first wiring lines; second wiring lines; third wiring lines; fourth wiring lines; and first and second storages. The first storage includes first memory cells arranged at intersections of the first wiring lines and the second wiring lines. Each of the third wiring lines is connected to any one of the first wiring lines. Each of the fourth wiring lines is pre-associated with a logical address specified by a host apparatus. The second storage includes second memory cells arranged at intersections of the third wiring lines and the fourth wiring lines. A resistance state of each of the second memory cells is set to a first resistance state or a second resistance state where a resistance value is lower than that in the first resistance state, according to a correspondence relationship between the logical address and the first wiring line.
申请公布号 WO2015041369(A1) 申请公布日期 2015.03.26
申请号 WO2014JP75760 申请日期 2014.09.19
申请人 KABUSHIKI KAISHA TOSHIBA 发明人 MARUKAME, TAKAO;MATSUZAWA, KAZUYA;NISHI, YOSHIFUMI;CHEN, JIEZHI;HIGASHI, YUSUKE;MITANI, YUUICHIRO
分类号 G11C16/06;G06F12/00;G06F12/02;G11C15/04;G11C16/02;G11C16/04 主分类号 G11C16/06
代理机构 代理人
主权项
地址