| 发明名称 |
Semiconductor Integrated Circuit |
| 摘要 |
A method of a semiconductor integrated circuit comprising a logic circuit including n storage elements (n is a positive integer) which can each store 1-bit information and an attack detection circuit, the method including detecting, by an error determination circuit, through a logic operation that k-bit or less errors (k is a positive integer) have occurred in n-bit codes stored in the n storage elements, and detecting, by a light irradiation detection circuit which includes light detection elements, that light has been irradiated to (k+1) or more of the n storage elements. It is determined that the logic circuit has been attacked from outside when the error determination circuit detects an error or the light irradiation detection circuit detects light irradiation. |
| 申请公布号 |
US2015089676(A1) |
申请公布日期 |
2015.03.26 |
| 申请号 |
US201414556160 |
申请日期 |
2014.11.30 |
| 申请人 |
Renesas Electronics Corporation |
发明人 |
Amanuma Yoshiyuki;Miyoshi Takanori |
| 分类号 |
G06F21/81;G06F21/64;H03K19/003 |
主分类号 |
G06F21/81 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. A method of a semiconductor integrated circuit comprising a logic circuit including n storage elements (n is a positive integer) which can each store 1-bit information and an attack detection circuit, the method comprising:
detecting, by an error determination circuit, through a logic operation that k-bit or less errors (k is a positive integer) have occurred in n-bit codes stored in the n storage elements; detecting, by a light irradiation detection circuit which includes light detection elements, that light has been irradiated to (k+1) or more of the n storage elements; and determining that the logic circuit has been attacked from outside when the error determination circuit detects an error or the light irradiation detection circuit detects light irradiation. |
| 地址 |
Kawasaki-shi JP |
