发明名称 METHOD OF FAILURE ANALYSIS
摘要 In some methods, a number of input data sets is provided for an integrated circuit (IC) model. A number of scores for the number of input data sets, respectively, are then determined based on probabilities of the respective input data sets resulting in a failure condition, which exists when the IC model fails to meet a predetermined yield criteria. A simulation order for the number of input data sets is then assigned according to the determined number of scores.
申请公布号 US2015089463(A1) 申请公布日期 2015.03.26
申请号 US201414492866 申请日期 2014.09.22
申请人 Taiwan Semiconductor Manufacturing Co., Ltd. 发明人 Kuo Chin-Cheng;Hsu Kmin;Hu Wei-Yi;Chan Wei Min;Kuan Jui-Feng
分类号 G06F17/50 主分类号 G06F17/50
代理机构 代理人
主权项 1. A simulation method, comprising: providing a plurality of input data sets for an integrated circuit (IC) model; performing a first simulation by applying a first of the plurality of input data sets to the IC model to generate a first simulation result, wherein the first input data set includes a first input device parameter with a first baseline parametric value and a second input device parameter with a second baseline parametric value; performing a second simulation by applying a second of the plurality of input data sets to the IC model to generate a second simulation result, wherein the second input data set includes the first input device parameter but with a first parametric value that differs from the first baseline parametric value and also includes the second input device parameter with the second baseline parametric value; determining a sensitivity of the IC model to the first input device parameter by comparing results of the first and second simulations; and defining a simulation order for remaining input data sets of the plurality of input data sets according to the sensitivity of the IC model to the first input device parameter.
地址 Hsin-Chu TW