发明名称 MULTIPLY ADD FUNCTIONAL UNIT CAPABLE OF EXECUTING SCALE, ROUND, GETEXP, ROUND, GETMANT, REDUCE, RANGE AND CLASS INSTRUCTIONS
摘要 A method is described that involves executing a first instruction with a functional unit. The first instruction is a multiply-add instruction. The method further includes executing a second instruction with the functional unit. The second instruction is a round instruction.
申请公布号 US2015088947(A1) 申请公布日期 2015.03.26
申请号 US201414559160 申请日期 2014.12.03
申请人 Intel Corporation 发明人 Anderson Cristina S.;Sperber Zeev;Rubanovich Simon;Eitan Benny;Gradstein Amit
分类号 G06F7/57;G06F5/01 主分类号 G06F7/57
代理机构 代理人
主权项 1. A processor, comprising: a functional unit having exponent difference calculation logic, a multiplier and an adder to support a multiply-add instruction, said functional unit also having a rounder to support a round instruction that specifies how many binary places a mantissa value is to be rounded to, said exponent difference calculation logic having a shifter to support execution of said multiply-add instruction and said round instruction.
地址 Santa Clara CA US