| 摘要 |
<p>Disclosed is a general-purpose SPI core using FPGA. According to the present invention, an SPI core, embedded in a device performing SPI communications, includes: a sync clock generating part generating a sync clock for synchronization in response to a clock polarity setting signal applied by a device when SPI communications is performed between the device and at least one other device performing the SPI communications; a counter generating count values determining a sampling timing of data and the number of bits of the data transceived through the SPI communications; and a SPI logic part receiving and then storing a control signal, including the clock polarity setting signal and a phase setting signal, from the device, and transceiving the data through the SPI communications between the device and at least one other device according to the stored phase setting signal and the counter values generated in the counter.</p> |
