| 摘要 |
PROBLEM TO BE SOLVED: To provide cross-coupled transistor layout techniques in restricted gate level layout architecture.SOLUTION: Each of a first P channel transistor, a first N channel transistor, a second P channel transistor and a second N channel transistor has a corresponding diffusion terminal electrically connected to a common node. Each of first, second, third, and fourth gate electrodes is formed to extend along any of a number of parallel oriented gate electrode tracks without physically contacting a gate level feature formed within any gate level feature layout channel associated with a gate electrode track adjacent to the gate electrode track. |
