发明名称 SEMICONDUCTOR DEVICE
摘要 A source interconnect and a drain interconnect are alternately provided between a plurality of transistor units. One bonding wire is connected to a source interconnect at a plurality of points. The other bonding wire is connected to a source interconnect at a plurality of points. In addition, one bonding wire is connected to a drain interconnect at a plurality of points. In addition, the other bonding wire is connected to a drain interconnect at a plurality of points.
申请公布号 US2015084135(A1) 申请公布日期 2015.03.26
申请号 US201414494409 申请日期 2014.09.23
申请人 Renesas Electronics Corporation 发明人 MIURA Yoshinao;NAKAMURA Takashi;DANNO Tadatoshi
分类号 H01L23/538;H01L27/02;H01L23/00;H01L27/088 主分类号 H01L23/538
代理机构 代理人
主权项 1. A semiconductor device comprising: a substrate; and a first transistor unit, a second transistor unit, and a third transistor unit which are formed in the substrate and are arranged side by side in this order in a first direction, wherein the first transistor unit, the second transistor unit, and the third transistor unit all include a plurality of transistors in which gate electrodes extend in the first direction, the semiconductor device further including: a first interconnect that extends between the first transistor unit and the second transistor unit in a second direction intersecting the first direction, and is connected to source electrodes of the plurality of transistors of the first transistor unit and source electrodes of the plurality of transistors of the second transistor unit; a second interconnect that is located on an opposite side to the first interconnect with the first transistor unit interposed therebetween, extends in the second direction, and is connected to drain electrodes of the plurality of transistors of the first transistor unit; a third interconnect that extends between the second transistor unit and the third transistor unit in the second direction, and is connected to drain electrodes of the plurality of transistors of the second transistor unit and drain electrodes of the plurality of transistors of the third transistor unit; a fourth interconnect that is located on an opposite side to the third interconnect with the third transistor unit interposed therebetween, extends in the second direction, and is connected to source electrodes of the plurality of transistors of the third transistor unit; a first bonding member that is connected to the first interconnect at a plurality of points; a second bonding member that is connected to the second interconnect at a plurality of points; a third bonding member that is connected to the third interconnect at a plurality of points; and a fourth bonding member that is connected to the fourth interconnect at a plurality of points.
地址 Kawasaki-shi JP