LOW POWER EXCESS LOOP DELAY COMPENSATION TECHNIQUE FOR DELTA-SIGMA MODULATORS

摘要

A delta sigma modulator with an input stage and an output stage. The input stage receives an analog input signal and an output of a first digital to analog converter (DAC). The input stage generates a processed error signal. An additional summation device receives the processed error signal. The output stage receives an output of the additional summation device and generates a delayed digital output signal. A differentiator and the first digital to analog converter (DAC) receive the delayed digital output signal as a feedback signal. A second DAC receives an output of the differentiator and provides an output to an additional negative feedback coefficient multiplier. The additional summation device receives an output of the additional negative feedback coefficient multiplier.

主权项

1. A delta sigma modulator comprising:
a first summation device configured to receive an analog input signal and an output signal from a first negative feedback coefficient multiplier; a first integrator configured to receive an output of the first summation device; a second summation device coupled to an output of the first integrator and configured to receive a signal from a second negative feedback coefficient multiplier; a third summation device coupled to an output of the second summation device and configured to receive a signal from a third negative feedback coefficient multiplier; a second integrator configured to receive an output of the third summation device; a quantizer configured to receive an output of the second integrator and generate a digital output signal; a delay element configured to receive the digital output signal and generate a delayed digital output signal; a first digital to analog converter (DAC) configured to provide an output signal to the first negative feedback coefficient multiplier and the second negative feedback coefficient multiplier, wherein the first DAC is configured to receive the delayed digital output signal, thereby forming a feedback loop; a second DAC configured to provide an output to the third negative feedback coefficient multiplier; and a differentiator configured to provide an output to the second DAC, wherein the differentiator is configured to receive the delayed digital output signal as a feedback signal.