发明名称 CACHE MEMORY SYSTEM AND PROCESSOR SYSTEM
摘要 [Problem] To be capable of improving the efficiency of accessing a large-capacity cache memory. [Solution] A cache memory system is provided with: a first cache memory of the kth order; a second cache memory having larger memory capacity than the first cache memory and using a non-volatile memory to be accessible faster than can a main memory be accessed; and a translation lookaside buffer for storing information on address translation from a virtual address issued by a processor to a physical address and information on a flag for recording whether data is stored in the second cache memory in page units larger in data amount than cache lines in which units the first cache memory is accessed.
申请公布号 WO2015041151(A1) 申请公布日期 2015.03.26
申请号 WO2014JP74128 申请日期 2014.09.11
申请人 KABUSHIKI KAISHA TOSHIBA 发明人 NOGUCHI HIROKI;FUJITA SHINOBU
分类号 G06F12/10;G06F12/08 主分类号 G06F12/10
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