发明名称 Demodulator and system for transmitting modulated information, in particular for radiofrequency identification tags
摘要 A demodulator including a delay line adapted for receiving an input signal at an input frequency, phase or frequency modulated by symbols with a duration equal to a period of the input signal or very close to that period. The delay line has Nd outputs producing Nd signals at the input frequency but with Nd different delays offset by ΔT relative to one another, Nd being an integer number greater than or equal to 1. The demodulator also includes a register of Nd latches each receiving a respective output of the delay line and a clock signal which is the input signal, in order to store the state of the outputs of the delay lines at the end of a period of the clock signal in the register. The content of the register represents a value of an input signal modulation symbol.
申请公布号 US8988144(B2) 申请公布日期 2015.03.24
申请号 US201013266826 申请日期 2010.05.04
申请人 Commissariat a l'Energie Atomique et aux Energies Alternatives 发明人 Lachartre David
分类号 H04L27/156;H04L27/233 主分类号 H04L27/156
代理机构 Baker & Hostetler LLP 代理人 Baker & Hostetler LLP
主权项 1. A demodulator comprising: a delay line adapted for receiving an input signal at an input frequency, phase or frequency modulated by symbols with a duration substantially equal to or equal to a period of the input signal, the delay line having Nd outputs producing Nd signals at the input frequency but with Nd different delays, Nd being an integer number greater than or equal to 1; and a register of Nd latches each receiving a respective output of the delay line and a clock signal which is the input signal, said Nd latches adapted to store a state of the outputs of the delay lines at the end of a period of the clock signal in the register, a content of the register representing a value of an input signal modulation symbol, wherein the delay line has a delay controlled by a locked loop, said locked loop comprising: a phase comparator receiving the input signal, phase or frequency modulated by the symbols, and one of the outputs of the delay line; andan integrator with a time constant greater than the duration of the symbols, receiving an output of the phase comparator and producing a delay line locking signal to lock the delays of the delay line according to an average value of the input frequency of the input signal, phase or frequency modulated by the symbols.
地址 Paris FR