Method of manufacturing Si-based high-mobility group III-V/Ge channel CMOS

摘要

A method can include: growing a Ge layer on a Si substrate; growing a low-temperature nucleation GaAs layer, a high-temperature GaAs layer, a semi-insulating InGaP layer and a GaAs cap layer sequentially on the Ge layer after a first annealing, forming a sample; polishing the sample's GaAs cap layer, and growing an nMOSFET structure after a second annealing on the sample; performing selective ICP etching on a surface of the nMOSFET structure to form a groove, and growing a SiO2 layer in the groove and the surface of the nMOSFET structure using PECVD; performing the ICP etching again to etch the SiO2 layer till the Ge layer, forming a trench; cleaning the sample and growing a Ge nucleation layer and a Ge top layer in the trench by UHVCVD; polishing the Ge top layer and removing a part of the SiO2 layer on the nMOSFET structure; performing a CMOS process.

主权项

1. A method of manufacturing a Si-based high-mobility Group III-V/Ge channel CMOS, comprising:
growing a Ge layer on a clean Si substrate using Ultrahigh Vacuum Chemical Vapor Deposition (UHVCVD); immediately placing the Si substrate in a Metal-Organic Chemical Vapor Deposition (MOCVD) reaction chamber after the Ge layer is formed; and growing a low-temperature nucleation GaAs layer, a high-temperature GaAs layer, a semi-insulating InGaP layer and a GaAs cap layer sequentially on the Ge layer after a first annealing, so as to form a sample; taking the sample out; polishing the GaAs cap layer; cleaning the MOCVD reaction chamber and the sample susceptor; placing the cleaned sample in the MOCVD reaction chamber; and growing an nMOSFET structure after a second annealing; performing selective Inductively Coupled Plasma (ICP) etching on a surface of the nMOSFET structure, etching from the nMOSFET structure downwards till the Ge layer to form a groove; and growing a SiO2 layer in the groove and the surface of the nMOSFET structure using Plasma Enhanced Chemical Vapor Deposition (PECVD); performing the ICP etching again, at a position where the selective etching has been performed, to etch the SiO2 layer till the Ge layer so as to form a trench; cleaning the sample; and growing a Ge nucleation layer and a Ge top layer in the trench using the UHVCVD; polishing the Ge top layer; and removing a part of the SiO2 layer on the nMOSFET structure; and performing a CMOS process on the nMOSFET structure and the Ge top layer to form source, drain, and gate structures.