Method and system for a run-time reconfigurable computer architecture

摘要

A reconfigurable computer architecture is disclosed. The reconfigurable computer architecture has a plurality of logic elements, a plurality of connection switching elements, and a plurality of volatile and/or non-volatile configuration random access memories (RAMs). Each of the configuration RAMs is electrically coupled to at least one of the plurality of logic elements or at least one of the connection switching elements.

主权项

1. A reconfigurable computer architecture, comprising:
a) a logic layer having:
1) a plurality of logic elements grouped into a plurality of macroblocks each containing at least two logic elements; and2) a plurality of connection switching elements; b) memory layer electrically coupled to the logic layer, the memory layer having:
1) a configuration storage associated with each of the plurality of macroblocks (MBs), wherein each configuration storage is configured for storing configuration bits and is electrically coupled to its associated macroblock using a through-silicon Via to enable reconfiguration.