Fused multiply-add rounding and unfused multiply-add rounding in a single multiply-add module

摘要

A computer processor including a single fused-unfused floating point multiply-add (FMA) module computes the result of the operation A*B+C for floating point numbers for fused multiply-add rounding operations and unfused multiply-add rounding operations. In one embodiment, a fused multiply-add rounding implementation is augmented with additional hardware which calculates an unfused multiply-add rounding result without adding additional pipeline stages. In one embodiment, a computation by the fused-unfused floating point multiply-add (FMA) module is initiated using a single opcode which determines whether a fused multiply-add rounding result or unfused multiply-add rounding result is generated.

主权项

1. A computer system comprising:
a memory; and a processor coupled to said memory; wherein said processor comprises a floating point multiply-add (FMA) module for receiving a first multiply term, a second multiply term, and an addition term; wherein in response to said processor receiving an unfused multiply-add opcode, said FMA module generates an unfused multiply-add rounding result by,
generating a first terminal partial product and a second terminal partial product from said first multiply term and said second multiply term,truncating said first terminal partial product to produce a truncated first terminal partial product,truncating said second terminal partial product to produce a truncated second terminal partial product, andcombining the truncated first terminal partial product, the truncated second terminal partial product, and said addition term; and wherein in response to said processor receiving a fused multiply-add opcode, said FMA module generates a fused multiply-add rounding result by,
generating the first terminal partial product and the second terminal partial product from said first multiply term and said second multiply term, andcombining the first terminal partial product, the second terminal partial product, and said addition term without truncating said first and second terminal partial products.