Circuit design support device, circuit design support method and program

摘要

A processing part inputs a behavior description code in which a write access array to be accessed to write and a read access array to be accessed to read are used. The processing part analyzes the behavior description code, and determines an order of using each write access address and an order of using each read access address when the behavior description code is executed. Further, the processing part performs either one of a write access order changing process to change the order of using the write access addresses when the behavior description code is executed based on the order of using the read access addresses and a read access order changing process to change the order of using the read access addresses when the behavior description code is executed based on the order of using the write access addresses.

主权项

1. A circuit design support device comprising:
a code inputting unit that inputs a behavior description code which describe behavior of a circuit which is a target of high level synthesis using a write access array identifying a plurality of write access addresses to be accessed to write to a memory array in the circuit and a read access array identifying a plurality of read access addresses to be accessed to read from a memory array in the circuit; an access order determining unit that analyzes the behavior description code, and determines an order of using write access addresses in the plurality of write access addresses when the behavior description code is executed and an order of using read access addresses in the plurality of read access addresses when the behavior description code is executed; and an access order changing unit that performs either one of a write access order changing process to change the order of using the write access addresses to write to the memory array in the circuit when the behavior description code is executed based on the order of using the read access addresses determined by the access order determining unit, and a read access order changing process to change the order of using the read access addresses to read from the memory array in the circuit when the behavior description code is executed based on the order of using the write access addresses determined by the access order determining unit, wherein the high level synthesis generates buffers based on timings of use of a write access address and a read access address having common address values, and the access order changing unit derives an order of using the write access addresses or the read access addresses by which a number of the buffers generated by the high level synthesis is decreased.