Encoding/decoding processor and wireless communication apparatus

摘要

An encoding/decoding processor includes a coprocessor that is dedicated to encoding and decoding processes, where the coprocessor comprises: a parameter register that stores externally given operation modes and the settings of generation polynomials; and a calculation circuit that operates on the basis of the operation modes and the generation polynomials and that performs calculations, which are required for the encoding and decoding processes, by a plurality of bits per cycle in a parallel manner, and the coprocessor further comprises memory controllers, which include: address generator circuits for outputting the addresses of the storage devices; FIFO circuits for temporarily storing data; and data packing circuits for making up predetermined numbers of bits of data for output.

主权项

1. An encoding/decoding processor built-in within a wireless communication apparatus for performing encoding and decoding processing of communication data, comprising a coprocessor used exclusively for the encoding and decoding processing, wherein
the coprocessor comprises: a parameter register which stores setting regarding an operation mode and a generation polynomial given from outside; a memory controller for making an access to a storage device that is built in or connected outside; and a calculation circuit which is operated based on the operation mode and the generation polynomial, and performs a calculation required for the encoding and decoding processing of a plurality of bits in 1 cycle, wherein the memory controller comprises: an address generator circuit which performs an operation for outputting an address on the storage device where data is read out and written independently according to a parameter given from outside; a FIFO (First In First Out) circuit which temporarily stores data written to the outputted address on the storage device or data read from the address; and a data packing circuit which outputs the data written to the outputted address on the storage device or the data read from the address by aligning number of bits thereof to number of bits defined in advance.