Constant frequency architectural timer in a dynamic clock domain

摘要

Implementations of the present disclosure involve an apparatus and/or method for providing a constant frequency timer signal for a microprocessor that operates with varying core clock signals. The apparatus and/or method utilizes a code generator, such as a gray code generator, operating on a reference clock signal that allows the constant frequency timer signal to be either faster or slower than the core clock frequency. More particularly, the apparatus and/or method may compute a difference between previous gray code samples and add the calculated difference to a software visible reference clock signal such that constant frequency timer signal may be faster or slower than the core clock signal. Through the use of the apparatus and/or method, a core clock signal may be reduced as needed to provide operational power savings to the microprocessor and the computing system employing the techniques described herein, while maintaining synchronization between the executing programs of the computing system.

主权项

1. A method for generating a timer signal in a microprocessor, the method comprising:
generating a reference code, the reference code configured to increment based on a reference clock signal; calculating a difference between a first value of the reference code and a second value of the reference code, the second value of the reference code occurring after the first value of the reference code; selecting from a plurality of inputs to a multiplexer based at least on the calculated difference between the first value of the reference code and the second value of the reference code; and incrementing a recursive timer signal based at least on the selected input to the multiplexer; wherein a timer signal circuit configured to increment the recursive timer signal based at least on the selected input to the multiplexer comprises:
the multiplexer comprising a plurality of inputs and an output;a counter latch comprising an input and an output;a first adder comprising a first input electrically connected to output of the multiplexer, a second input electrically connected to the output of the counter latch and an output electrically connected to the input of the counter latch;a multiplier comprising an input and an output, the multiplier configured to multiply a value on the input by two; anda second adder comprising a first input, a second input and an output.