| 主权项 |
1. A self-refresh control circuit for controlling a self-refresh operation of a memory device, comprising:
a self-refresh control logic block configured to control the memory device to perform the self-refresh operation; and an initial refresh control block configured to activate the self-refresh control logic block in an initialization period of the memory device, wherein the initial refresh control block comprises:
a pulse generation unit configured to generate a reset pulse wherein the reset pulse is activated when a reset signal is deactivated; anda self-refresh period signal generation unit configured to activate a self-refresh period signal in response to an activation of the reset pulse and deactivate the self-refresh period signal in response to the activation of a clock enable signal, wherein the self-refresh control logic block is activated in a period where the self-refresh period signal is activated. |
