发明名称 |
Biasing scheme for large format CMOS active pixel sensors |
摘要 |
An image sensor includes circuitry compensating for voltage drops in a VSS line. The image sensor includes a plurality of photoreceptors arranged in a pixel array having a number of column lines, and read-out circuitry on the column lines. The read-out circuitry provides substantially equal currents on each column line so as to compensate for voltage drops in the VSS line and provide more accurate pixel signals. The image sensor also includes circuitry for filtering noise from a voltage supply line, and for providing hard and/or soft reset operations. |
申请公布号 |
US8988568(B2) |
申请公布日期 |
2015.03.24 |
申请号 |
US200812216430 |
申请日期 |
2008.07.03 |
申请人 |
Micron Technology, Inc. |
发明人 |
Nakamura Junichi;Takayanagi Isao |
分类号 |
H04N3/14;H04N5/365;H04N5/357;H04N5/3745;H04N5/378 |
主分类号 |
H04N3/14 |
代理机构 |
Dickstein Shapiro LLP |
代理人 |
Dickstein Shapiro LLP |
主权项 |
1. An image sensor comprising:
a pixel array including a plurality of column lines; a plurality of load transistors, each coupling a respective one of the column lines to a ground line; and a plurality of circuits, each respectively coupled to a gate of a load transistor, the plurality of circuits applying a substantially equal gate-source voltage to the gates of each of the load transistors. |
地址 |
Boise unknown |