Endurance aware error-correcting code (ECC) protection for non-volatile memories

摘要

Embodiments of the invention relate to endurance-aware ECC protection for memories (e.g., phase change memories). According to one embodiment, a method includes calculating first metadata for data bits and second metadata for ECC bits which protect the data bits and the first metadata. Embodiments can include one or more first metadata bits (for the data bits), and one or more second metadata bits (for the ECC bits). An additional level of ECC protection protects the second metadata. In one embodiment, the wear-reduction modifications applied to the data bits and the ECC bits are different, and can be tailored to the behavior of the bits. According to one embodiment, the endurance-aware ECC protection described herein reduces wear due to accesses to memories while addressing the complications wear-reduction mechanisms introduce to error detection and correction systems.

主权项

1. A method comprising:
calculating an error-correcting code (ECC) bit for shifted data bits and a metadata bit, the metadata bit indicating a shift to the data bits to be written to a non-volatile memory; calculating a second ECC bit for a second metadata bit, the second metadata bit indicating an inversion of the ECC bit; and storing, in the non-volatile memory, the shifted data bits, the metadata bit, the inverted ECC bit, the second metadata bit, and the second ECC bit.