Semiconductor device

摘要

A semiconductor device includes at least two semiconductor chips each including a plurality of data input/output pads, a data memory portion structured so as to read/write data through the plurality of data input/output pads, a test result input/output pad, and a test circuit for controlling a first test mode that decides data read from the data memory portion and outputs the decision from the test result input/output pad and a second test mode that decides data read from the data memory portion, inputs test result of another semiconductor chip from the test result input/output pad and outputs a synthesized test result of the test result of the chip itself and the test result of the other semiconductor chip from a specified part of the plurality of data input/output pads, and a plurality of data input/output terminals each connected with different data input/output pads.

主权项

1. A semiconductor device, comprising:
a plurality of semiconductor chips each comprising:
a plurality of first pads and a second pad;a memory cell array;a first test circuit coupled to the memory cell array and generating a first test result signal in response to first test data of the memory cell array;a first input/output buffer coupled to the first test circuit and the second pad, the first input/output buffer supplying the first test result signal to the second pad when the each of the semiconductor chips is in a first test mode, the first input/output buffer generating a second test result signal therein in response to one or ones of third test result signals supplied from the second pad when the each of the semiconductor chips is in second test mode; anda second test circuit receiving the first test result signal and the second test result signal, performing a logic operation on logic levels of the first test result signal and the second test result signal to generate a fourth test result signal and supplying the fourth test result signal to first one of the first pads when the each of the semiconductor chips is in the second test mode, wherein the second pad of one of the semiconductor chips is electrically coupled to the second pad of each of remaining one or ones of the semiconductor chips and the one of the semiconductor chip is in the second test mode and the remaining one or ones of the semiconductor chips are in the first test mode such that the first input/output buffer of the remaining one or ones of the semiconductor chips supplies the first test result signal to the second pad of the one of the semiconductor chips as one of the third test result signals, wherein each of the semiconductor chips further comprises:
a third pad; anda second input/output buffer coupled to one of the first pads and the memory array, the second input/output buffer supplying the memory cell array with the first test data supplied from the third pad when the each of the semiconductor chips is in the first test mode, the second input/output buffer supplying the third pad with the first test data supplied from a second one of the first pads when the each of the semiconductor chips is in second test mode, and wherein the third pad of the one of the semiconductor chips is electrically coupled to the third pad of each of the remaining one or ones of the semiconductor chips.