发明名称 |
High-density inter-package connections for ultra-thin package-on-package structures, and processes of forming same |
摘要 |
An apparatus includes a coreless mounting substrate and an interposer disposed on the coreless mounting substrate with a chip disposed in a recess in the interposer and upon the coreless substrate. The apparatus may include an inter-package solder bump in contact with an interconnect channel in the interposer, and a top chip package including a top package substrate and a top die disposed on the top package substrate. The top package substrate is in contact with the inter-package solder bump. |
申请公布号 |
US8987896(B2) |
申请公布日期 |
2015.03.24 |
申请号 |
US201012890345 |
申请日期 |
2010.09.24 |
申请人 |
Intel Corporation |
发明人 |
Cheah Bok Eng;Periaman Shanggar;Ooi Kooi Chi |
分类号 |
H01L23/48;H01L23/498;H01L23/00;H01L25/065;H01L25/10 |
主分类号 |
H01L23/48 |
代理机构 |
|
代理人 |
Greaves John N. |
主权项 |
1. An apparatus, comprising:
a coreless mounting substrate; an interposer disposed on the coreless mounting substrate, wherein the interposer includes:
a die side and a land side that is parallel planar to the die side;a chip recess that communicates to the die side and the land side, wherein the chip recess projects a footprint onto the coreless mounting substrate;an interconnect channel that passes through the interposer, wherein the interconnect channel is electrically coupled to the coreless substrate by contact with a substrate bump; anda trace in the coreless mounting substrate, wherein the recess footprint is asymmetrically located with respect to a symmetry line that equally bisects the coreless substrate. |
地址 |
Santa Clara CA US |