发明名称 Metal semiconductor alloy contact with low resistance
摘要 A method of forming a semiconductor device is provided that includes forming a gate structure on a channel portion of a semiconductor substrate, forming an interlevel dielectric layer over the gate structure, and forming a opening through the interlevel dielectric layer to an exposed surface of the semiconductor substrate containing at least one of the source region and the drain region. A metal semiconductor alloy contact is formed on the exposed surface of the semiconductor substrate. At least one dielectric sidewall spacer is formed on sidewalls of the opening. An interconnect is formed within the opening in direct contact with the metal semiconductor alloy contact.
申请公布号 US8987078(B2) 申请公布日期 2015.03.24
申请号 US201314028957 申请日期 2013.09.17
申请人 International Business Machines Corporation;GLOBAL FOUNDRIES, Inc. 发明人 Yu Jian;Johnson Jeffrey B.;Li Zhengwen;Pei Chengwen;Hargrove Michael
分类号 H01L21/336;H01L21/8238;H01L29/66;H01L21/285;H01L21/768;H01L23/485;H01L29/49;H01L29/51 主分类号 H01L21/336
代理机构 Scully, Scott, Murphy & Presser, P.C. 代理人 Scully, Scott, Murphy & Presser, P.C. ;Cai Yuanmin
主权项 1. A method of forming a semiconductor device comprising: forming a gate structure on a channel portion of a semiconductor substrate, wherein a source region and a drain region are present on opposing sides of the channel portion of the semiconductor substrate; forming an interlevel dielectric layer over the gate structure; forming an opening to at least one of the source region and the drain region through the interlevel dielectric layer to an exposed surface of the semiconductor substrate containing at least one of the source region and the drain region, wherein said forming of the opening comprises forming an etch mask over the dielectric layer including initial openings having a first width, etching the interlevel dielectric layer with an anisotropic etch that is selective to the exposed portion of the semiconductor substrate, and increasing the width of the initial openings to a second width to provide the openings to at least one of the source region and the drain region; forming a metal semiconductor alloy contact on the exposed surface of the semiconductor substrate; forming at least one dielectric sidewall spacer on sidewalls of the opening overlying a portion of the metal semiconductor alloy region; and forming an interconnect within the opening in direct contact with the metal semiconductor alloy contact.
地址 Armonk NY US