| 发明名称 |
LAYOUT OPTIMIZATION FOR INTEGRATED CIRCUIT DESIGN |
| 摘要 |
A method for laying out a target pattern includes assigning a keep-out zone to an end of a first feature within a target pattern, and positioning other features such that ends of the other features of the target pattern do not have an end within the keep-out zone. The target pattern is to be formed with a corresponding main feature and cut pattern. |
| 申请公布号 |
US2015082259(A1) |
申请公布日期 |
2015.03.19 |
| 申请号 |
US201414552095 |
申请日期 |
2014.11.24 |
| 申请人 |
Taiwan Semiconductor Manufacturing Company, Ltd. |
发明人 |
CHEN HUANG-YU;Hou Yuan-Te;Kao Yu-Hsiang;Hsieh Ken-Hsien;Liu Ru-Gun;Lu Lee-Chung |
| 分类号 |
G06F17/50 |
主分类号 |
G06F17/50 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. A method for laying out a target pattern, the method comprising:
positioning a first feature in a main pattern, the first feature including a first end and a first cut pattern; assigning a keep-out zone to an end of the first feature and the first cut pattern; and positioning a second feature in the target pattern such that a second end of the second feature does not lie within the keep-out zone. |
| 地址 |
Hsin-Chu TW |
