发明名称 PARALLEL FLOOD-FILL TECHNIQUES AND ARCHITECTURE
摘要 Flood-fill techniques and architecture are disclosed. In accordance with one embodiment, the architecture comprises a hardware primitive with a software interface which collectively allow for both data-based and task-based parallelism in executing a flood-fill process. The hardware primitive is defined to do the flood-fill function and is scalable and may be implemented with a bitwise definition that can be tuned to meet power/performance targets, in some embodiments. In executing a flood-fill operation, and in accordance with an example embodiment, the software interface produces parallel threads and issues them to processing elements, such that each of the threads can run independently until done. Each processing element in turn accesses a flood-fill hardware primitive, each of which is configured to flood a seed inside an N×M image block. In some cases, processing element commands to the flood-fill hardware primitive(s) can be queued and acted upon pursuant to an arbitration scheme.
申请公布号 US2015077422(A1) 申请公布日期 2015.03.19
申请号 US201414550214 申请日期 2014.11.21
申请人 INTEL CORPORATION 发明人 Gluska Alon;Gupta Niraj;Hagog Mostafa;Reif Dror
分类号 G06T1/20 主分类号 G06T1/20
代理机构 代理人
主权项 1. A device, comprising: a flood-fill hardware primitive configured to receive and update an input flood map for a given image block to be flood-fill processed to include final pixel positions to be flooded thereby providing an updated flood map; and a processing element configured to execute a flood fill routine in accordance with the updated flood map.
地址 SANTA CLARA CA US