REGISTER MAPPING WITH MULTIPLE INSTRUCTION SETS

摘要

A processor core supports execution of program instruction from both a first instruction set and a second instruction set. An architectural register file 18 containing architectural registers is shared by the two instruction sets. The two instruction sets employ logical register specifiers which for at least some values of those logical registers specifiers correspond to different architectural registers within the architectural register file 18. A first decoder 4 for the first instruction set and a second decoder 6 for the second instruction set serve to decode the logical register specifiers to a common register addressing format. This common register addressing format is used to supply register specifiers to renaming circuitry 10 for supporting register renaming in conjunction with a physical register file 16 and an architectural register file 18.

主权项

1. Apparatus for processing data comprising:
a register file having a plurality of registers for storing operand values; first decoder circuitry configured to decode program instructions of a first instruction set; and second decoder circuitry configured to decode program instructions of a second instruction set; wherein program instructions of said first instruction set include first logical register specifiers; program instructions of said second instruction set include second logical register specifiers; said first decoder circuitry is configured to map said first logical specifiers using a first mapping to a common address format; said second decoder circuitry is configured to map said second logical specifiers using a second mapping to said common address format; and said second mapping is divergent from said first mapping such that at least some values used as both a first logical register specifier and a second logical register specifier map to different registers.