发明名称 SEMICONDUCTOR MEMORY DEVICE
摘要 A semiconductor memory device according to an embodiment comprises a memory cell and a control circuit, the control circuit performing write of data to the memory cell. The memory cell includes a second resistance varying layer sandwiched between a first resistance varying layer and a third resistance varying layer. The second resistance varying layer has a resistance value which is smaller than that of the other resistance varying layers. The control circuit applies to the memory cell a first voltage pulse, and then applies to the memory cell a second voltage pulse that has a rise time which is shorter than that of the first voltage pulse.
申请公布号 US2015078063(A1) 申请公布日期 2015.03.19
申请号 US201414444350 申请日期 2014.07.28
申请人 KABUSHIKI KAISHA TOSHIBA 发明人 ICHIHARA Reika;FUJII Shosuke;MIYAGAWA Hidenori;ISHIKAWA Takayuki
分类号 G11C13/00;H01L45/00 主分类号 G11C13/00
代理机构 代理人
主权项 1. A semiconductor memory device, comprising a memory cell and a control circuit, the memory cell including: a first electrode; a first resistance varying layer formed on the first electrode; a second resistance varying layer formed on the first resistance varying layer and having a resistance value which is smaller than that of the first resistance varying layer; a third resistance varying layer formed on the second resistance varying layer and having a resistance value which is larger than that of the second resistance varying layer; and a second electrode formed on the third resistance varying layer, and the control circuit applying to the memory cell a first voltage pulse, and then applying to the memory cell a second voltage pulse that has a polarity which is identical to that of the first voltage pulse and that has a rise time which is shorter than that of the first voltage pulse, thereby performing write of data to the memory cell.
地址 Minato-ku JP