发明名称 |
METHOD AND APPARATUS FOR FORMING AN INTEGRATED CIRCUIT WITH A METALIZED COUPLING CAPACITOR |
摘要 |
An integrated circuit includes a plurality of metal layers of bit cells of a memory cell array disposed in a first metal layer and extending in a first direction, a plurality of word lines of the memory cell array disposed in a second metal layer and extending in a second direction that is different from the first direction, and at least two conductive traces disposed in a third metal layer substantially adjacent to each other and extending at least partially across the memory cell array, a first one of the at least two conductive traces coupled to a driving source node of a write assist circuit, and a second conductive trace of the at least two conductive traces coupled to an enable input of the write-assist circuit, where the at least two conductive traces form at least one embedded capacitor having a capacitive coupling to the bit line. |
申请公布号 |
US2015076575(A1) |
申请公布日期 |
2015.03.19 |
申请号 |
US201314031057 |
申请日期 |
2013.09.19 |
申请人 |
Taiwan Semiconductor Manufacturing Co., Ltd. |
发明人 |
WU Ching-Wei;KAO Wei-Shuo;CHEN Chia-Cheng;CHEN Kuang Ting |
分类号 |
H01L27/11;H01L29/94 |
主分类号 |
H01L27/11 |
代理机构 |
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代理人 |
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主权项 |
1. An integrated circuit, comprising:
a plurality of bit cells of a memory cell array disposed in a first metal layer and extending in a first direction; a plurality of word lines of the memory cell array disposed in a second metal layer and extending in a second direction that is different from the first direction; and at least two conductive traces disposed in a third metal layer substantially adjacent to each other and extending at least partially across the memory cell array, a first one of the at least two conductive traces coupled to a driving source node of a write assist circuit, and a second conductive trace of the at least two conductive traces coupled to an enable input of the write-assist circuit, wherein the at least two conductive traces form at least one embedded capacitor having a capacitive coupling to the bit line. |
地址 |
Hsin-Chu TW |