发明名称 Memory Module with Integrated Error Correction
摘要 A memory system includes a memory module that supports error detection and correction (EDC) in a manner that relieves a memory controller or processor of some or all of the computational burden associated with EDC. individual EDC components perform EDC functions on subsets of the data, and share data between themselves using relatively short, fast interconnections.
申请公布号 US2015082119(A1) 申请公布日期 2015.03.19
申请号 US201414475619 申请日期 2014.09.03
申请人 Rambus Inc. 发明人 Ware Frederick A.;Best Scott C.
分类号 H03M13/15;G06F11/10;H03M13/00 主分类号 H03M13/15
代理机构 代理人
主权项 1. A memory module comprising: memory components to communicate data signals and syndrome signals; error-detection components each having: a first interface connected to a respective subset of the memory components to receive a respective subset of the data signals and a respective subset of the syndrome signals;error-detection logic to detect errors in the respective subset of the data signals using the respective subset of the syndrome signals; anda second interface to transmit the respective subset of the data signals; and a module connector coupled to the second interfaces to communicate the data signals.
地址 Sunnyvale CA US